In recent years, a liquid crystal display that adopts a CG (Continuous Grain) silicon liquid crystal panel has been developed. The CG silicon liquid crystal panel refers to a liquid crystal panel that adopts TFTs (Thin Film Transistors) formed of a CG silicon film, as switching elements. In the CG silicon, grain boundaries are arranged regularly, and the CG silicon has a continuous structure at atomic-level. Therefore, in the CG silicon, electrons can move at high speed and thus a driving integrated circuit can be mounted on a substrate of a liquid crystal panel. By this, a reduction in cost and miniaturization of a device due to a reduction in the number of necessary components are advanced. Note that in the following a liquid crystal display that adopts a CG silicon liquid crystal panel is referred to as a “CG silicon liquid crystal display”.
FIG. 2 is a block diagram showing the overall configuration of a CG silicon liquid crystal display. The liquid crystal display has a liquid crystal panel 100 including a source driver (video signal line drive circuit) 300, a gate driver (scanning signal line drive circuit) 400, a display unit 500, and a charge pump circuit 600; and a display control circuit 200. The display unit 500 includes a plurality of (n) source bus lines (video signal lines) SL1 to SLn; a plurality of (m) gate bus lines (scanning signal lines) GL1 to GLm; and a plurality of (n×m) pixel formation portions respectively provided at intersections of the plurality of source bus lines SL1 to SLn and the plurality of gate bus lines GL1 to GLm.
The display control circuit 200 outputs an analog video signal AV, and a source start pulse signal SSP, a source shift clock signal SCK, a gate start pulse signal GSP, and a gate shift clock signal GCK, for controlling timing to display an image on the display unit 500, based on an image signal DAT, a horizontal synchronizing signal Hsync, and a vertical synchronizing signal Vsync which are provided from an external source and a clock signal (hereinafter, referred to as a “source clock signal”) CK generated by a clock generator.
The source driver 300 receives the analog video signal AV, the source start pulse signal SSP, and the source shift clock signal SCK which are outputted from the display control circuit 200 and applies a driving video signal to each of the source bus lines SL1 to SLn to display an image on the display unit 500. Here, in the source driver 300, in each horizontal scanning period, taking in of the source start pulse signal SSP is started upon the first rise of the source shift clock signal SCK after the source start pulse signal SSP rises. In conventional common liquid crystal displays, in order that taking in of a source start pulse signal SSP in the source driver 300 can be normally started, as shown in FIG. 5, a hold period is provided before the source start pulse signal SSP rises and a setup period is provided after the source start pulse signal SSP rises. Note that the hold period as used in the description refers to a period provided between the point in time when the source shift clock signal SCK falls and the point in time when the source start pulse signal SSP rises, so as to ensure that the source start pulse signal SSP rises after the source shift clock signal SCK falls. The setup period refers to a period provided between the point in time when the source start pulse signal SSP rises and the point in time when the source shift clock signal SCK rises, so that the logic level of the source start pulse signal SSP is certainly a high level at the point in time when the source shift clock signal SCK rises.
However, in the case of a CG silicon liquid crystal display, since in the liquid crystal panel 100 the delay of the source start pulse signal SSP is sufficiently larger than that of the source shift clock signal SCK, in the display control circuit 200, as shown in FIG. 6, even when a source shift clock signal SCK and a source start pulse signal SSP are generated without setting a hold period, taking in of the source start pulse signal SSP is properly performed in the source driver 300.
In recent years, a reduction in the frame area of such a CG silicon liquid crystal display has been carried out. Hence, when a source shift clock signal SCK and a source start pulse signal SSP are generated without setting a hold period in the above-described manner, the delay of the source start pulse signal SSP relative to the source shift clock signal SCK may not be sufficiently large and thus trouble may occur in image display. Consequently, there is a need to set a hold period when a source shift clock signal SCK and a source start pulse signal SSP are generated in the display control circuit 200.
An example is provided. There is a liquid crystal display in which the cycle of a source clock signal CK is set to T, the cycle of a source shift clock signal SCK is set to 3 T, and a hold period Th and a setup period Ts should respectively satisfy the following equations (1) and (2). Note that FIG. 7 is a signal waveform diagram for such a liquid crystal display.0.5 T≦Th<T  (1)2 T<Ts≦2.5 T  (2)
According to the aforementioned example, the hold period Th and the setup period Ts are not an integral multiple of the cycle T of the source clock signal CK. Conventionally, in such a case, the frequency of the source clock signal CK is increased or both-edge drive of a clock is performed.    [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-173173